A Max 2.3μA Quiescent Current External Capacitorless Low-Dropout Regulator

Abstract

The paper presents an external capacitorless low-dropout regulator (LDO) with a ultra-low quiescent current for system-on-chip (SoC) in portable electronic applications. A sub-1-V, nanopower voltage reference ensures the low power consumption of the LDO system. The external capacitorless design allows the LDO to be fully integrated on chip, which not only saves area and cost, but also eliminates bond-wire effects. In order to compensate the lack of large off-chip output capacitor, a two-stage error amplifier with nested Miller compensation is applied to ensure system stability. Besides, a small on-chip output capacitor and a slew-rate enhancement circuit are attached to improve transient response. The proposed LDO is designed and simulated in 55 nm process. Compared with prior works, this LDO has the minimum output capacitor of 5pF and the ultra-low quiescent current of 2.3μA with load regulation of 0.41mV/mA and figure-of-merit (FOM) of 1.95.