A matrix model for redefining and testing NoC interconnect shorts

Abstract

Network-on-chip (NoC) has currently considered as a holistic solution over traditional and global bus-based system-on-chip (SoC) interconnections. However, NoC interconnects experience a subset of manufacturing faults- shorts, opens, and stuck-ats. A limitation of prior works on testing shorts on interconnects of a NoC is that interconnects are tested without coexistent open faults. The works then fail to detect all shorts if a relaxation is made on this assumption. A fast matrix based test strategy that tests and diagnoses shorts with and without coexistent opens on NoC interconnects is proposed. Proposed strategy is scalable irrespective of NoCs and evaluated in terms of test time, test criteria, and performance metrics. Both 100% and near 100% fault coverages are achieved on explicit and implicit testing of shorts respectively. However, 100% test coverage is achieved in either of the cases.