Highly reliable and power efficient NOC interconnects

Abstract

Network on chip (NOC) architecture interconnects consume significant amount of power, have a large propagation delay and are susceptible to error due to deep sub-micron (DSM) noise. Major challenge that NOC design expected to face is related to intrinsic reliability. By incorporating error control coding schemes along the NOC interconnects, NOC architectures are able to provide correct functionality in the presence of different transient noise source. In this paper we present a novel coding scheme that increase the reliability of the NOC where the area is reduced by 19% and the consumed power by NOC interconnects is decreased by 51%. Butterfly fat tree architecture consumes the minimum power as compared to other NOC architectures.