A MATLAB to VHDL Conversion Toolbox for Digital Control

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This paper will describe the development of a prototype software toolbox that can analyze and process a Simulink block diagram model in order to produce a VHDL representation of the model. The derived VHDL model will consist of a combination of behavioural, RTL and structural definitions mapped directly from the Simulink model. This approach may enable a user to develop and simulate a digital control algorithm using Mat/ab and once complete, convert this to VHDL code. This would then be synthesized into digital logic hardware for implementation on devices such as FPGAs (Field Programmable Gate Arrays) and ASICs (Application Specific Integrated Circuits).