A Low-Voltage SRAM Sense Amplifier With Offset Cancelling Using Digitized Multiple Body Biasing

Abstract

With continued CMOS technology scaling down, transistors exhibit higher degrees of variation and mismatch, resulting in a larger offset voltage. A large offset voltage will enlarge bitline swing, increasing dynamic power consumption during a read operation and degrading the sensing decision correct rate and operation speed. Thus, the offset voltage is the most critical metric for static random access memory sense amplifiers (SAs), mainly arising from transistor threshold voltage mismatch. Here we propose an offset-cancelling technique with digitized multiple body biasing. In this scheme, SA transistor threshold voltage mismatch is compensated by adjusting the body bias voltage digitally and repeatedly. Simulation results in 130-nm CMOS technology show that the proposed calibration technique can reduce the standard deviation of the offset voltage by over four times comparing to a conventional SA, with about 6.5% and 1.6% area power overhead of a 6-kbit prototype chip introduced.