Abstract
In this paper, we present the design of a novel low voltage (1.8 V) low-power (230 /spl mu/W) CMOS operational amplifier. It utilises the adaptive biased technique in order to minimize the quiescent power consumption of its input stage without degradation of the dynamic performance. A class-AB output stage allows current control. The op-amp has been designed with input and output full swing (rail-to-rail) and constant transconductance over the input common mode range. The DC gain is 73 dB. The gain bandwidth is 1.5 MHz (PM=77/spl deg/) and the slew rate is greater than 15 V//spl mu/s, for a 100 pF/1 k/spl Omega/ load. The minimum operating supply voltage is 1.5 V. The circuit performance has been compared with some literature solutions, showing much better characteristics.
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