A low-voltage low-power 25 Gb/s clock and data recovery with equalizer in 65 nm CMOS

Abstract

A novel low-power low-jitter 25 Gb/s clock and data recovery (CDR) circuit with equalizer that can work at an ultra-low supply voltage of 0.6 V is proposed and implemented in a 65 nm CMOS process. A two-tank transformer-feedback technique is proposed in the 25 GHz LC-tank VCO to improve the phase noise performance at low supply voltage. Forward-body biasing (FBB) technique is proposed in the low-voltage signal path to reduce the threshold voltage of the transistors, thus increasing the signal amplitude and achieving low BER. The measurement results show that the CDR and equalizer can work under 0.6 V with 0.23ps/4.62ps (rms/pk-pk) of recovered clock jitter. The measured power consumption of the CDR with the equalizer is 48.8 mW (1.95 mW/Gb/s).