A Low-power Reconfigurable Readout Circuit with Large DC Offset Reduction for Neural Signal Recording Applications

Abstract

This paper presents a fully reconfigurable readout circuit including a chopper-stabilized neural amplifier and a successive approximation register (SAR) analog-to-digital converter (ADC) for neural signal recording applications. Since the target neural signals - action potentials (APs) and local field potentials (LFPs) differ in the peak amplitude while occupying different frequency bandwidths, gain, and bandwidth reconfigurability would be advantageous in improving power and noise performance. The readout circuit is designed in 180 nm standard CMOS technology. It achieves the mid-band gain of 50.3 dB in the frequency band of 0.1 Hz - 250 Hz to detect the LFPs, and 63.4 dB in 267 Hz - 20.8 kHz for detecting the APs. The neural amplifier consumes a total power of 1.54 µW and 1.94 µW for LFP and AP configurations, respectively. The input-referred noises have been achieved as 0.97 µV rms (0.1 Hz - 250 Hz), and 0.44 µV rms (250 Hz - 5 kHz), leading to a noise efficiency factor (NEF) of 1.27 and 1.21, for the two configurations, respectively. It rejects the generated large DC offset up to 40 mV at the electrode-tissue interface, by implementing a DC servo loop (DSL). The offset voltage with the DSL becomes 0.23 mV, which is acceptable for the neural experiments. Enabling the impedance boosting loop, the DC input impedance is found to be within the range of 1.77 - 2.27 GΩ, introducing the reconfigurability in impedance for matching with the electrode impedance. The SAR-ADC having a varying sampling frequency ranging from 10 - 40 ksamples/s demonstrates to digitize the APs and the LFPs with the resolution from 8 - 10 bits. The entire AFE provides good compatibility to record the neural signal while lowering the large DC offset down to 0.23 mV.