A low-power high-speed two-stage dynamic comparator with a new offset cancellation technique in 90 nm CMOS technology

Abstract

A new high-speed low-power two-stage dynamic comparator is proposed, using a new offset cancellation technique for the resolution enhancement. The input-referred offset voltage equations are derived, and the mechanism of offset cancellation is analytically explained. The simulation results for the 90 nm CMOS technology demonstrates that the proposed comparator can work up to 4 GHz clock frequency while the delay time and standard deviation in offset voltage are 44.6 ps and 518 μV, respectively. The power consumption is 341 μW @ 4 GHz with a 1.2 V supply voltage.