A low-power, high-speed open-loop residue amplifier for pipelined ADCs with digital calibration

Abstract

This paper presents a new open-loop residue amplifier for low power, high speed pipelined ADCs with digital calibration. In order to reduce the variance of the amplifier's gain from the influences of temperature and technology, a replica amplifier and a differential difference amplifier (DDA) are used to control the transconductances of the amplifier's input transistors. Because common-mode control circuit is not needed, the stability and response speed of the amplifier are improved. Designed in a 0.18 mum CMOS technology, the open-loop amplifier consumes only 5.6 mW at a 1.8 V supply voltage. Simulation results show that the variance of gain and the linearity of the output meet the requirements of the calibration algorithm. The pipelined ADC using this open-loop residue amplifier achieves 12-bit, 40MS/s conversion through carrying out digital calibration.