Abstract
In this article, a rail-to-rail low-power amplifier is presented based on stacking inverter-based amplifiers. The output voltages of each inverter-based amplifier are converted to a current and then mirrored to the output so that a rail-to-rail output is achieved. Besides, extensive simulations have been carried out to show the effect of drain-source voltage on the intrinsic gain of a transistor. Based on these simulations, a minimum supply voltage is chosen to achieve high open-loop gain and low closed-loop gain error. All the simulations are carried out in a commercially available 0.18 μm CMOS technology. The proposed amplifier achieves 88 dB open-loop gain. It is exploited in a capacitively-coupled amplifier structure. The closed-loop gain is 40 dB in the bandwidth of 0.1 Hz to 10 kHz when the power consumption is 0.54 μW at a 1.2 V supply voltage. The total input-referred noise is 4.7 μV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rms</sub> in the whole bandwidth. The proposed neural amplifier achieved 0.02 SEF in the bandwidth from 200 Hz to 10 kHz. The proposed amplifier achieved a rail-to-rail output swing while the SEF is among the best reported SEF in the literature. Besides, to show the robustness of the proposed structure in the presence of process and mismatch variation, 500 Monte Carlo simulations are carried out. The PSRR and CMRR mean values are 89 dB and 68 dB, respectively. Finally, the proposed neural amplifier area consumption is 0.03 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> without pads.
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