Abstract
Power dissipation problem becomes a dominant factor in the state-of-the-art IC design. In this paper, we use accurate delay and power models to construct buffered routing trees with consideration of power optimization under timing constraints. Moreover, with the supply voltage goes down, the supply voltage variation becomes an important part of total supply voltage, and make the traditional timing estimation inaccurate and unreliable. Our algorithm takes the supply voltage variation into account to obtain better solutions. Experimental results show, our method can save 42.8% and 75.9% of power dissipation and total buffer area, respectively. Moreover, with the consideration of supply voltage variation, 12.0% power dissipation and 31.6% total buffer area will be saved compared with the worst case IR-drop estimation, and more reliable solutions are obtained compared with the cases not considering supply voltage variation.
Published Version
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