A low-power and small chip-area fractional-N digital PLL with combination of DPI and TDC

Abstract

This paper presents a novel fractional-N digital PLL structure with a digitally controlled phase interpolator (DPI) and a time-to-digital converter (TDC). In this structure, a short bit-width DPI and a short bit-width TDC are combined to achieve high phase resolution and low in-band phase noise. Moreover, since the DPI readily achieves 360° phase range and the TDC provides good linearity, no extra complex calibration is needed, which simplifies the design and saves power and chip area. Designed in a 55-nm CMOS technology, the proposed digital PLL achieves −103 dBc/Hz in-band phase noise at 2.4 GHz output frequency. It consumes 2.4 mW from a 1.2-V supply and occupies 0.18 mm2 active chip area.