Abstract
A low-noise self-oscillating mixer (SOM) operating from 7.8 to 8.8 GHz is described in this paper. Three different components, the oscillator, the mixer core, and the LNA transconductor stage are assembled in a stacked configuration with full dc current-reuse from the VCO to the mixer to the LNA. The LC-tank oscillator also functions as a double-balanced IF load to the low-noise mixer core. A theoretical expression is given for the conversion gain of the SOM taking into account the time-varying nature of the IF load impedance. Measurements show that the SOM has a minimum DSB noise figure of 4.39 dB and a conversion gain of 11.6 dB. Its input P1 dB is - 13.6 dBm and its output P1 dB is - 2.97 dBm, while its IIP3 and OIP3 are - 8.3 dBm and + 3.3 dBm respectively. The chip consumes 12 mW of dc power and it occupies an area of 0.47 mm2 without pads.
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