Abstract
The paper presents a fully integrated multiphase output low-jitter CMOS phase-locked loop for 1.25 Gb/s to 6.25Gb/s wireline SerDes transmitter clocking. The self-biased bandwidth technology with simplified structure is applied to reduce the sensitivity to process variations. A differential charge pump which has property of low mismatch is proposed. The self-biased technology is used to make the bandwidth track the division ratio, which will improve suppression of VCO noise at higher output frequency. The simulation results under 65nm show good jitter performance.
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