A Low-Error and Area-Time Efficient Fixed-Width Booth Multiplier

Abstract

In this paper, the authors developed a new methodology for designing a lower-error and area-time efficient 2s-complement fixed-width Booth multiplier that receives two n-bit numbers and produces an n-bit product. By properly choosing the generalized index and binary thresholding, a better error-compensation bias was derived to reduce the truncation error. Since the proposed error-compensation bias is realizable, the constructing low-error fixed-width Booth multiplier is area-time efficient for VLSI implementation. Finally, the proposed fixed-width Booth multiplier was applied to speech signal processing. The simulation results show that the performance is superior to that using the direct-truncation fixed-width Booth multiplier