Abstract
This paper presents a second-order multi-bit delta-sigma modulator. The modulator uses feed-forward architecture to relax the linearity requirement of the integrators. An asynchronous successive approximation register (SAR) type analog-to-digital converter (ADC) is employed to implement both a 4-bit quantizer and a summing adder without using an additional amplifier. In order to reduce the distortion resulted from the multi-bit feedback digital-to-analog converter (DAC), split time integration technique is used. The prototype modulator was fabricated in a 45-nm CMOS technology and occupies 235 m. The proposed delta-sigma modulator achieves 81.8 dB dynamic range (DR), 76.8 dB signal-to-noise and distortion ratio (SNDR) for a 5 kHz signal bandwidth. It consumes 850 W with a 1.1 V supply.
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