Abstract
This paper presents a low complexity macroblock (MB) level H.264/AVC rate control (RC) algorithm from system-level design viewpoint for video encoder hardware implantation. MB pipeline structure and data reuse efficiency are simultaneously take into consideration. In order to improve the data processing efficiency, hardware encoder usually adopts zigzag scanning MB encoding sequence order instead of raster one. The proposed low-cost RC algorithm resolves the problem of data dependency without increasing processing latency. Moreover, the proposed algorithm adopts a new MB level mean absolute difference (MAD) prediction method to improve the MAD prediction efficiency in G012 proposal. Linear prediction method in G012 resulting in lower complexity and memory requirements not only reduce the complexity of RC algorithm but also the memory buffer. Simulation results show only 32%, 68%, and 88% hardware cycles are desired for QCIF, CIF and D1 format video real-time coding respectively in the proposed RC algorithm compared with G012, while maintaining the same PSNR compared with G012.
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