A Low Voltage and Low Power Flip-flop Design Using Virtual VDD Scheme

Abstract

A novel low voltage and low power truesingle-phase flip-flop (FF) design is proposed in this paper. It is adapted from conventional Set-Reset latch based FF design and achieves circuit simplification by using virtual VDD scheme. The optimization measure leads to a new design providing better various performances. Based on post layout simulation results using the TSMC CMOS 180 ㎚ technology, the proposed design outperforms the conventional TGFF by 68.7% in energy consumption (at 25% switching activity).