A low-power True Single Phase Clock scan cell design for VLSI testing

Abstract

Abstract The shrinkage of the feature size of a transistor has increased the need for testing of System on Chips (SoCs). Excessive power consumption during test mode may cause reliability issues and/or may result in manufacturing yield loss. To solve these issues, a True Single Phase Clocked (TSPC) scan cell is proposed for low power consumption during the shift operation in test mode. The average power minimization of the TSPC scan cell is achieved by reducing the switching transitions inside the scan cell. TSPC scan cell also blocks the redundant transitions propagating from the scan chain to the combinational block of the design. Simulation results show that 31.42% reduction in average power is observed in TSPC scan cell compared to existing scan cell without much increase in peak power consumption.