A low-power sub 100 ns 256K bit dynamic RAM

Abstract

A 256K-word /spl times/ 1-bit NMOS dynamic RAM using 2-/spl mu/m design rules and MoSi/SUB 2/ gate technology is described. A marked low-power dissipation of 170 mW (5 V V/SUB cc/, 260-ns cycle time) has been achieved by using a partial activation scheme. Optimized circuits exhibit a typical CAS access time of 34 ns. For the purpose of optimizing circuit parameters, an electron beam tester was successfully applied to observe the internal timing of real chips. Laser repairable redundancy with four spare rows and four spare columns is implemented for yield improvement.