Abstract
In wireless communication networks, the necessity for high-speed data rates has increased in emerging 5G application areas. The Power Amplifier (PA) topologies reported to date achieved desired Power Added Efficiency (PAE) and linearity. However, these harmonically tuned switching PAs are less appealing for broadband applications as they are restricted to narrow bandwidth (BW). Therefore, to meet the 5G requirements, the challenge of designing a PA with improved efficiency and linearity for a dynamic range of BW becomes critical for PA designers. Recently developed Class-J PA topology can obtain good efficiency while maintaining linearity for wide BW applications. This research work presents a methodology to design a 5 GHz Class-J mode PA topology using Silterra 0.13 μm CMOS technology. This research's main objectives are to determine the Ropt of the transistor and design a proper Output Matching Network (OMN) for obtaining Class-J PA operation to make it suitable for 5G wireless applications. The simulation results represent that the designed Class-J PA provides 27 dBm of maximum power output with a maximum power gain of 13.7 dB and the small-signal gain of 17 dB for a BW of around 500 MHz with a 5 V power supply into a 50Ω load.
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