A Low Power High Speed 15T FinFET-GDI Based Hybrid Full Adder Using 18 nm Technology

Abstract

AbstractOver the years, adder has become an essential component in any digital system, especially in modern processor architectures. Several different adders have been designed and proposed by researchers to perform the task of addition. In this paper, a low-power high speed 15T Fin Field Effect Transistor (FinFET)-Gate Diffusion Input (GDI) based Hybrid Full Adder (HFA) is proposed. The design is implemented at 1, 0.9, and 0.8 V power supply using 18 nm FinFET technology at 27 \(^\circ \)C temperature with the help of the Cadence Virtuoso tool. The various performance parameters like average power dissipation, maximum propagation delay, and Power Delay Product (PDP) of the proposed adder are compared with existing adder topologies like Conventional Complementary Metal Oxide Semiconductor (CCMOS-Mirror) adder, Complementary Pass Logic (CPL) adder, Double Pass Transistor Logic (DPL) adder, Swing Restored Complementary Pass Logic (SRCPL) adder, Transmission Gate adder (TGA), Transmission Function adder (TFA), and 10T Gate Diffusion Input (GDI) adder in terms of average power dissipation, maximum propagation delay and PDP. It has been observed that the proposed adder has the lowest PDP amongst all adders discussed in this paper for 1, 0.9, and 0.8 V power supply. The Process Corner and the Monte Carlo analysis are also performed for the proposed adder at a supply voltage of 1 V.KeywordsFin Field Effect Transistor (FinFET)Gate Diffusion Input (GDI)Very Large Scale Integrated Circuits (VLSI)Arithmetic and Logic Unit (ALU)Complementary Metal Oxide Semiconductor (CMOS)