A Low Power, High Conversion gain CMOS Inductorless Frequency Doubler for 1.25 - 20 GHz Frequency Synthesis in mm-wave Receivers

Abstract

Frequency doublers present an effective technique for μ-wave/mm-wave frequency generation using frequency multiplication. In this work, a 20 GHz frequency is generated using a 10 GHz phase locked loop (PLL) that improves its power and area efficiency. The fundamental 10 GHz signal and its sufficiently strong second harmonic at 20 GHz are generated simultaneously using a PLL and a mixer-based frequency doubler. The proposed mixer uses an inductorless fully-differential active-inductor topology to reduce the area with marginal tradeoff in phase noise. The frequency synthesizer was designed and implemented in CMOS 65 nm technology. The doubler is integrated with a 10 GHz LC-VCO based PLL having an active area of 390×520 μm2 (without pads), with a phase noise of −115 dBc/Hz at 10 MHz offset frequency and consumes 36.72 mW power from 1.2V power supply, one of the lowest among the reported literature. The mixer has a maximum conversion gain (CG) of 5.46 dB, 1-dB compression point (P −1dB ) of −2.5 dBm and an input-referred third-order intercept point (IIP3) of −3.2 dBm. The proposed inductorless mixer-based doubler occupies an active area of 55×35 μm2 and it adds < 1.5 dB phase noise at 20 GHz. The attained phase noise makes it an attractive choice for microwave and mm-wave links in mm-wave receivers.