Abstract
Pseudo random bit generator is widely used in BIST for test pattern generation. Typical pseudo random bit generator adopts linear feedback shift register (LFSR) as its basic circuit. Dynamic LFSR (DLFSR[1]) which has better cryptographic properties with respect to typical LFSR consumes more power. This paper forwards a low power DLFSR (LDLFSR) circuit which achieves comparable performance with less power consumption. Typical LFSR, a DFLSR[1], a LDLFSR are compared on randomness property and inviolability property. Multi-layer perceptron neural networks are used to test these LFSRs¿ inviolability property. Result shows that LDLFSR keeps comparable performance with a 7% power reduction and a 5.6% area reduction.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
