Abstract
Pseudo Random Bit Generator (PRBG) is a key element to protect the data in various cryptography applications during transmission. To prove more secure among different previous pseudo random bit generator methods like Linear Feedback Shift Register (LFSR), Linear Congruential Generator (LCG), coupled LCG (CLCG), and Dual Coupled LCG (dual-CLCG) the modified Dual coupled LCG (MDCLCG) is implemented. This method used is to generate a pseudo random bit with less area occupation and with single clock delay. In this paper three different ways of adder topologies ripple carry adder (RCA), carry skip adder (CSKA) and carry increment adder (CIA) are implemented in the place of modulo carry save adder to analyze the area, power and speed performance of the modified Dual Coupled LCG design using Verilog-HDL and prototyped on FPGA device Spartan3E XC3S500E.
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