A low power charge-redistribution SAR ADC with a monotonic switching procedure

Abstract

This paper proposed a novel low power charge-redistribution successive approximation analog-to-digital converter (CR-SAR ADC). During its conversion, the reference voltage is only half of the ADC's dynamic range. The monotonic switching procedure is used to further reduce the switching energy of the SAR ADC. Matlab simulations are performed to compare the switching energies in the proposed and previous low power SAR ADCs. A 11-bit 40-KS/s SAR ADC using the proposed technique is designed and simulated with UMC 0.18 µm 1P6M CMOS technology. The designed SAR ADC achieves 10.75 effective number of bit (ENOB) and consumes 10µW.