A low power and high linearity UWB low noise amplifier (LNA) for 3.1–10.6 GHz wireless applications in 0.13 μm CMOS process

Abstract

In this paper, a low power ultra-wideband (UWB) CMOS LNA was designed exploiting source inductive degeneration technique operating in the frequency range of 3.1–10.6GHz. In order to achieve low noise figure and high linearity simultaneously, a modified three-stage UWB LNA with inter-stage inductors was proposed. Forward Body-Biased (FBB) technique was used to reduce threshold voltage and power consumption at the first and third stages. The second stage is a push–pull topology exploiting the complementary characteristics of NMOS and PMOS transistors to enhance the linearity performance. The proposed LNA was simulated in standard 0.13μm CMOS process. A gain of 19.5±1.5dB within the entire band was exhibited. The simulated noise figure (NF) was 1–3.9dB within the bandwidth. A maximum simulated third-order input intercept point (IIP3) of 4.56dBm while consuming 4.1mW from a 0.6 power supply was achieved. The simulated input return loss (S11) was less than −5dB from 4.9 to 12.1GHz. The output return loss (S22) was below −10.6dB and S12 was better than −70.6dB.