A low-power 128-MHz VCO for monolithic PLL ICs

Abstract

The phase-locked loop (PLL) is implemented by 2- mu m bipolar-CMOS (BiCMOS) technology. The power dissipation of the PLL and the voltage-controlled oscillator (VCO) are 100 mW at 64 MHz and 25 mW for 1-128 MHz clock frequencies, respectively. The linearity of the VCO is +or-0.5% and the temperature stability is +or-50 p.p.m./ degrees C. The center frequency of the VCO is accurately set by using one fixed external resistor. The VCO has an advantage of noise insensitivity. To achieve these features, the VCO design uses an emitter-coupled multivibrator with a built-in timing capacitor and a controlled oscillation loop gain. The PLL can be applied not only to timing recovery for data transmission, but also to frequency synthesis and self-clocking for data recording.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>