Design of Voltage-Controlled Oscillator with Single-Event Transients Tolerance

Abstract

Voltage controlled oscillators (VCOs) have been shown to be a critical block of single-event transient (SET) response in mixed-signal circuits used for satellite communication such as the phase-locked loop (PLL). After analyzing the mechanism of frequency to be drifted, a novel structure of VCO consisting of SET hardened bias generator and two cross coupled ring oscillator (RO) cell was designed. This VCO was designed in 130-nm process which had been proposed to minimize the drift of the frequency caused by SET pulse, thus to improve the stability of circuit. Spice based simulation was utilized to demonstrate the improvement of proposed structure. The result showed that the present VCO had a significant improvement by comparing with conventional differential VCO in reducing the control voltage and oscillating frequency drift. During the iron implantation, the PLL with proposed VCO will remain locked and its frequency drift was reduced by 95.58%.