Abstract
High-density microelectrode arrays allow the neuroscientist to study a wider neurons population, however, this causes an increase of communication bandwidth. Given the limited resources available for an implantable silicon interface, an on-fly data reduction is mandatory to stay within the power/area constraints. This can be accomplished by implementing a spike detector aiming at sending only the useful information about spikes. We show that the novel non-linear energy operator called ASO in combination with a simple but robust noise estimate, achieves a good trade-off between performance and consumption. The features of the investigated technique make it a good candidate for implantable BMIs. Our proposal is tested both on synthetic and real datasets providing a good sensibility at low SNR. We also provide a 1024-channels VLSI implementation using a Random-Access Memory composed by latches to reduce as much as possible the power consumptions. The final architecture occupies an area of 2.3 mm2, dissipating 3.6 µW per channels. The comparison with the state of art shows that our proposal finds a place among other methods presented in literature, certifying its suitability for BMIs.
Highlights
The most popular and used spike detector methods are those based on a non-linear energy operator and its variations providing the best trade-off between resource requirements and detection performance, and are more appropriate for an implantable solution [16,17]
We investigate and propose a new spike detector based on the novel energy operator called amplitude slope operator (ASO) proposed by Zhang, Z et al [20], and a threshold based on our noise estimate WA
Instead of focusing on maximizing all detection performance, a good practice is to increase the number of spikes rightly detected (TPR) over false-alarm rate (FAR) and Accuracy since an off-chip sorting algorithm will be responsible for extracting the spike features and discarding all the false positives
Summary
The most popular and used spike detector methods are those based on a non-linear energy operator and its variations providing the best trade-off between resource requirements and detection performance, and are more appropriate for an implantable solution [16,17] These operators estimate the instantaneous frequency and amplitude of the signal to be processed. Setting aside the choice of the spike detector and the hardware approach (ASIC, embedded system, etc.), from a hardware implementation point of view, a crucial aspect that unites all the algorithms is the large use of flip-flops required to store and process the data, in particular the enhancement block, that might limit the increase of the channels to be processed because of the limited resource available To overcome this limit, we implemented a low-power random access memory (RAM) by using latches; more details are given in Section 2 [21].
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