Abstract
A fault tolerant, radiation hardened Clock and Data Recovery (CDR) architecture is presented for high-energy physics and space applications. The CDR employs a novel soft-error tolerant Voltage Controlled Oscillator (VCO) and includes a high-speed feed-forward path, which stabilizes the CDR by compensating for an additional pole introduced in the VCO in order to harden it against ionizing particles. The CDR has a data rate of 2.56 Gb/s and uses In-Phase/Quadrature (IQ) clocks in combination with a frequency detector (FD) to increase the pull-in range. The circuit was designed in a 65 nm CMOS technology and has a core power consumption of only 34 mW. The circuit was tested while subjected to heavy-ions with a Linear Energy Transfer (LET) up to 62.5 MeV cm -2 mg -1 . Additionally, the circuit was irradiated using X-rays up to a Total Ionizing Dose (TID) of 350 Mrad.
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