A Low Noise and Low Power CMOS Image Sensor with Pixel-level Correlated Double Sampling

Abstract

A low noise and low power CMOS image sensor (CIS) with pixel-level correlated double sampling (CDS) is proposed. As the pixel readout circuit using source follower is major readout noise and power consumption source in the conventional CIS structure, the proposed new structure removes the source follower and performs pixel-level CDS and comparing. The proposed CIS is integrated with 240 times 180 pixel array. A pixel fill factor is 32% and its pitch is 8.4 mum. The test chip was fabricated with CMOS 0.35-mum process and its power consumption is 18 mW with 3.3 V occupying 8.1 mm2.