Abstract
In this brief, a non-least positive form (NLP) based modular multiplication method that combines Karatsuba and schoolbook multiplication is applied in Montgomery modular multiplication, which saves 2 base multiplications compared to Karatsuba-only designs and allows pipeline structure to make most use of the parallelism in large modular multiplications. Based on this method, 256-bit and 512-bit modular multipliers are constructed with 3-way and 4-way NLP multipliers on FPGA platform. Implemented on Virtex-6, the 256-bit design can perform a modular multiplication in 62.6 ns and only requires 3.5K LUTs and 24 DSPs, which exhibits low-latency and low-cost among previous works.
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