A low jitter wide tuning range phase locked loop with low power consumption in 180nm CMOS technology

Abstract

This paper describes a design of phase locked loop system suitable for clock synchronization and generation. PLLs with high speed, low noise and wide bandwidth with fast acquistion time are preferred. A PFD with low dead zone, charge pump with passive low pass filter and a low noise, wide tuning VCO are integrated in the PLL system. A novel current controlled oscillator(ICO) with wide tuning range of 420MHz to 3.1GHz and low phase noise of -66.83 dBc/Hz @ 1MHz offset is designed. The PFD modeled is a D-latch based digital PFD and conventional charge pump with second order loop filter is used. Integrating this ICO in a PLL system offers low jitter and wide bandwidth. This PLL system is simulated and tested in CADENCE UMC180nm technology. The results prove that the lock-in range of PLL is 500MHz to 1.5GHz with a maximum jitter of 27.1ps, maximum pull-in time is 420ns and the maximum power consumed by this PLL system is 343.7μW at 1.5GHz.