A low jitter self-calibration PLL for 10Gbps SoC transmission links application

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A 2.5-GHz 8-phase phase-locked loop (PLL) was proposed for 10 Gbps system on chip (SoC) transmission links application. The proposed self-calibration method can adjust the multi-band voltage control oscillator (VCO) to compensate for process, voltage and temperature (PVT) variations. The small KVCO can reduce the effect of power/ ground (P/G) and substrate noise. The PLL is implemented in 0.13 mum CMOS technology. The PLL output jitter is 18.55 ps (p-p) where the reference clock jitter is 20 ps (p-p). The total power dissipation is 21 mW at 2.5-GHz and the core area is 0.08 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .