A low jitter 110MHz 16-phase delay locked loop based on a simple and sensitive phase detector

Abstract

A 16-phases low jitter delay locked loop, DLL, based on a simple phase detector is proposed in 0.35μm CMOS process. Moreover, a sensitive phase detector is introduced which detects small phase differences of input and generated clock signals. High sensitivity, besides the simplicity reduces the dead zone of the phase detector and yields a better clock jitter, consequently. A new strategy of common mode level setting is proposed for differential delay elements which no longer introduce extra parasitics on output nodes. Also, the input differential clock is carefully transferred inside the chip to considerably reduce the noise effect of power supply. Post-Layout simulation results confirm the RMS jitter of about 6.7ps at 20MHz and 2ps at 100MHz input clock frequency when the 3.3v power supply is subject to 75mv peak-to-peak noise. Total power consumption reaches from 7.5mW to 16.5mW when the operating frequency increases from 20MHz to 100MHz.