A low-cost, fault-tolerant and high-performance router architecture for on-chip networks

Abstract

The router as the main component of on-chip networks has a key role in making connections between the processing cores. Thus, regarding the unreliable silicon, preserving the routers in operational states has a great effect on the network performance. Among different units of a router, the input ports including the buffers have a high fault occurrence probability due to consuming a large portion of a router's area. This paper presents a fault tolerant router architecture which utilizes a new decoupled resource sharing approach for the input ports. The proposed architecture highly improves the overall reliability and network performance against multiple permanent faults in the input ports even incorporating a non-fault tolerant routing algorithm. Furthermore, the new resource sharing approach decreases the packet latencies while the faulty links exist in the network. The experimental results show that all improvements are achieved at the cost of a very low hardware overhead compared to the baseline router while the proposed router architecture reaches to greatest Silicon Protection Factor (SPF) as a metric compared to all previous designs.