Abstract

The ever-shrinking size of a transistor has made Network on Chip (NoC) susceptible to faults. A single error in the NoC can disrupt the entire communication. In this paper, we introduce Defender, a fault-tolerant router architecture, that is capable of tolerating permanent faults in all the parts of the router. We intend to employ structural modifications in baseline router design to achieve fault tolerance. In Defender we provide the fault tolerance to the input ports and routing computation unit by grouping the neighboring ports together. Default winner strategy is used to provide fault resilience to the virtual channel arbiters and switch allocators. Multiple routes are provided to the crossbar to tolerate the faults. Defender provides improved fault tolerance to all stages of routers as compared to the currently prevailing fault tolerant router architectures. Reliability analysis using silicon protection factor (SPF) and Mean Time to Failure (MTTF) metrics confirms that our proposed design Defender is 10.78 times more reliable than baseline unprotected router and then the current state of the art architectures.

Highlights

  • Advancements in semiconductor technology [1], [2] allow us to fabricate silicon dies with billions of transistors

  • Each module that is used for grouping of ports consists of MUXes and an Error Control Unit (ECU) which utilize the NoCAlert checkers [34] for the detection of faults in the input port

  • We evaluated the defender our proposed router architecture in terms of area overhead, reliability analysis as Silicon Protection Factor (SPF), and Mean Time to Failure (MTTF)

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Summary

INTRODUCTION

Advancements in semiconductor technology [1], [2] allow us to fabricate silicon dies with billions of transistors. The fault that lasts only for a few clock cycles and temporarily affects the operation of the circuit is called transient fault. Many researchers have already worked to tolerate the faults occurring in NoC router and links [14]–[18]. These approaches do not provide fault tolerance to each component of router.

OVERVIEW OF BASELINE NETWORK ON CHIP ROUTER
PROBLEM STATEMENT
DEFENDER THE PROPOSED FAULT TOLERANT ROUTER ARCHITECTURE
DEFENDER
RESULTS AND ANALYSIS
RELIABILITY IMPROVEMENT COMPARISON USING SPF
FIT ESTIMATION OF RELIABLE ROUTER
MTTF OF PROPOSED ROUTER
CONCLUSION
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