A low complexity digital unit for scalar linear interpolation and compression

Abstract

A linear interpolator with compressed output and its alternative version that supports error correction are presented in this paper. The interpolation devices can be driven by an Analog/Digital Converter (ADC) that accepts as input, low frequency signals, like sensor values. The proposed interpolation methods can correct ADC linearity errors and increase the dynamic resolution of an ADC or they can reconstruct a signal from fewer samples in non-uniform distance. If the input signal is partially exponential or logarithmic then, specific correction rules can be employed to achieve a lower signal quantization error. These rules are based on simple operations like shifts and comparisons and thus, they can be implemented using low complexity hardware. Spline, Linear, Quadratic interpolation, popular compression tools and reference signals are used to evaluate the experimental results. The proposed architecture is scalar since multiple interpolators can be connected in series. A 3-stage interpolator with 9-bit input and 12-bit typical output resolution was tested with sinusoidal input. The Signal to Noise and Distortion Ratio (SNDR) of the ADC that has been used was increased up to the double. The proposed method was also tested using a pressure sensor, an acoustic signal and image reconstruction leading to Mean Square Error (MSE) that is up to 10 times lower. The achieved compression ratio, ranges between 11% and 76%. The implementation complexity of a one stage interpolator with 9-bit input resolution requires 583 Logic Elements (LE) i.e., less than 3% of the LEs that exist in an Altera Cyclone III EP3C25N Field Programmable Gate Array (FPGA).