A look-ahead synthesis technique with backtracking for switching activity reduction in low power high-level synthesis

Abstract

Research work done has shown that power consumption in digital integrated circuits can be effectively reduced by reducing the switching activity occurring on the functional modules. High-level synthesis of digital integrated circuits for low power often optimizes the switching activity during the two main synthesis processes, operation scheduling and module binding, which are usually performed one control step at a time in two separated stages. As the two processes are strongly interdependent, separate optimization of switching activity in a step-by-step manner frequently leads to sub-optimal solutions. In this paper, we propose a novel look-ahead synthesis technique with backtracking for the reduction of switching activity in low power high-level synthesis, which not only performs the scheduling and binding simultaneously in an integrated manner using a weighted bipartite technique, but also employs a branch and bound approach with look-ahead evaluation of switching activity for one or more control steps. The look-ahead technique generates multiple schedulings and bindings at the same time in one control step and uses each of them to generate more schedulings and bindings for the next one or more control steps. The best scheduling and binding pattern is then used for backtracking, therefore, effectively reducing the probability for the solutions to fall into local minimum. We tested the look-ahead algorithm with several published benchmarks and the experimental results obtained show that the switching activity can be reduced significantly, with an average of more than 50% reduction in switching activity for the tested benchmarks.