A logic difference generator with spare cells consideration for ECO synthesis

Abstract

As the advance of IC manufacturing, the IC complexity is getting more and more complicated. Lots of existing designs and intellectual property (IP) are widely reused. Different from remaking a whole new chip, reusing existing designs or IP can release the pressure of time-to-market and save money. By utilizing logic difference technique, IC designer can identify differences between old and new circuits and output several engineering change orders (ECO) for functional change. Therefore, the quality of engineering changer orders will affect the functional change result. To the best of our knowledge, the success or failure of the functional change is depended on spare cells not the number of engineering change orders. Hence, this paper proposed a logic difference technique which considers the distribution of spare cells primarily. The experimental results show that our proposed algorithm has more engineering change orders than traditional logic difference technique, but it can achieve better result in wirelength and success rate after functional ECO.