Unified approach for simultaneous functional and timing ECO

Abstract

Engineering change order (ECO) is a technique commonly used in the later integrated circuit design stages to reduce redesign efforts and time-to-market. ECO problems are generally categorised according to functional changes (functional ECO) or timing violations (timing ECO). This study differs from conventional approaches in its adoption of a solution that involves unifying functional ECO with timing ECO. The authors applied the concept of virtual nodes to the problem of transforming timing ECO into functional ECO. In addition to buffer insertion and gate sizing, the authors developed a novel detour reduction method for the repair of timing violation paths. Technology mapping is used to facilitate the selection of spare cells, through the generation of various revisions for each ECO. The unified ECO problem is then solved using a novel modification of the Hungarian matching algorithm. Experiment result demonstrates the efficacy of the proposed approach at solving both types of ECO simultaneously.