Abstract
This paper presents an area-efficient time-domain CMOS smart temperature sensor using a curvature compensation oscillator for linearity enhancement with a −40 to 120 °C temperature range operability. The inverter-based smart temperature sensors can substantially reduce the cost and circuit complexity of integrated temperature sensors. However, a large curvature exists on the temperature-to-time transfer curve of the inverter-based delay line and results in poor linearity of the sensor output. For cost reduction and error improvement, a temperature-to-pulse generator composed of a ring oscillator and a time amplifier was used to generate a thermal sensing pulse with a sufficient width proportional to the absolute temperature (PTAT). Then, a simple but effective on-chip curvature compensation oscillator is proposed to simultaneously count and compensate the PTAT pulse with curvature for linearization. With such a simple structure, the proposed sensor possesses an extremely small area of 0.07 mm2 in a TSMC 0.35-μm CMOS 2P4M digital process. By using an oscillator-based scheme design, the proposed sensor achieves a fine resolution of 0.045 °C without significantly increasing the circuit area. With the curvature compensation, the inaccuracy of −1.2 to 0.2 °C is achieved in an operation range of −40 to 120 °C after two-point calibration for 14 packaged chips. The power consumption is measured as 23 μW at a sample rate of 10 samples/s.
Highlights
Temperature sensors are commonly used for temperature sensing and are widely applied in measurements, instrumentation, and control systems
Two-point calibration was fulfilled by performing linear curve fitting with the digital outputs of −40 °C and 80 °C, which were chosen to minimize error
A nearly five-fold improvement in accuracy is achieved when compared with the simulation inaccuracy without curvature compensation
Summary
Temperature sensors are commonly used for temperature sensing and are widely applied in measurements, instrumentation, and control systems. CMOS digital process, the chip size was only 0.09 mm, and the measured error was ±0.6 °C after two-point calibration within a −40 to 60 °C temperature range. Based on a linear MOS operation, another ultra-low power of 405 nW@1 k samples/s CMOS smart sensor with a differential temperature sensing delay generator was proposed [8]. The core area is 0.01 mm in a 65-nm CMOS, and the power consumption is 150 μW@10 k samples/s Later, another FPGA-based version for one-point calibration support and circuit size reduction was proposed [10]. With one-point calibration, a frequency-to-digital-converter-based smart sensor that involves using a multiphase clock was proposed to achieve an inaccuracy of −2.7–2.9 °C within a range of −40 °C to 110 °C [11].
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