A library based on deep neural networks for modeling the degradation of FinFET SRAM performance metrics due to aging

Abstract

FinFET SRAM cells suffer from front-end wearout mechanisms, such as bias temperature instability and hot carrier injection. In this paper, we built a library based on deep neural networks (DNNs) to speed up the process of simulating FinFET SRAM cells' degradation. This library consists of two parts. The first part calculates circuit configuration parameters, wearout parameters, and the other input variables for the DNN. The second part calls for the DNN to determine the shifted circuit performance metrics. A DNN with more than 99% accuracy is achieved with training data from standard Hspice simulations. The correctness of the DNN is also validated in the presence of input variations. With this library, the simulation speed is one hundred times faster than Hspice simulations. We can display the cell's degradation under various configurations easily and quickly. Also, the DNN-based library can help protect intellectual property without showing users the circuit's details.