A Hysteresis Controlled Resolution for Level Crossing Sampling ADC

Abstract

A Variable Resolution Level Crossing Sampling(LCS) based Analog-to-Digital Converter(ADC) for current generation low power devices is designed. Field programmable hysteresis controls the quantisation step and the resolution of the designed ADC. Depending on hysteresis, two modes of operation are proposed, (i) Power Saving Mode (ii) Performance Mode. In power saving mode, 20%-25% power is saved by trading off 1–2 bit resolution. Comparatively, in performance mode, higher resolution is achieved at the cost of higher power. This architecture is suitable for sampling of sparse input signals. The hysteresis comparators are biased in subthreshold region. The proposed circuit, designed with 0.8V supply in $0.18\mu\mathrm{m}$ CMOS technology, consumes total power of around 580–760 nW for 1kHz sinusoidal input and achieves an effective resolution of 6–7 bits.