Abstract
Most watermarking schemes for intellectual property (IP) protection embed authorship information at a single design abstraction level. Effective means to directly verify the watermark distributed at the downstream designs are lacking, particularly after the IP core is packaged into chip. This paper proposes a hybrid scheme for watermarking sequential designs. At behavioral level, the finite state machine (FSM) is watermarked by interweaving the watermark bits into the outputs of its existing and unspecified transitions. During the Design-for-Testability (DfT) process, the scan chain that incorporates the watermarked FSM as one of the test kernels is further watermarked to provide a second level of protection. It enables the watermark on the FSM to be publicly detectable by the legitimate end users off chip via the scan test. Experimental results on ISCAS'89 and LGSynth'93 benchmark circuits show that the watermarked circuits have acceptably low overheads with stronger authorship proof.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
