Abstract
This paper presents a new finite control set model predictive control strategy that, contrary to conventional approaches, achieves (i) zero steady-state error in the converter’s AC current, and (ii) both fixed and lower harmonic spectrum, similar to that achieved by pulse width modulation based control schemes. These characteristics are attractive for medium and high voltage applications where high dv/dt is prohibitive and reduced switching losses are a must, or in applications that use passive filters and where a spread harmonic spectrum can cause resonances. The proposed strategy achieves dynamic results similar to those of conventional predictive control and a steady-state performance similar to that of a modulated control strategy. To do so, the strategy utilizes a modulated integral action to incorporate an input restriction into a conventional predictive control cost function. A grid-connected cascaded H-Bridge multilevel inverter is used to validate the strategy. Simulated and experimental results in both steady and transient states are presented to verify the proposed strategy’s performance in the converter.
Highlights
T HE efficient use of low-voltage semiconductors in highvoltage, high-power applications has been made possible thanks to multilevel converters [1]
In the case of the converter output voltage, its harmonic spectrum is concentrated around six-times the carrier frequency given that a PS-PWM scheme is used [4], [41]. These results show that the distribution of the harmonic spectrum is defined only by the modulation scheme used to generate the proposed input restriction
The input restriction of the proposed Finite Control Set Model Predictive Control (FCS-MPC) is evaluated with respect to the voltage vector obtained from a linear controller with integral action
Summary
T HE efficient use of low-voltage semiconductors in highvoltage, high-power applications has been made possible thanks to multilevel converters [1]. These topologies have a series of advantages over traditional two-level converters such as lower device switching frequency, lower commonmode voltage, reduced dv/dt stress, and a low THD, among others [2], [3]. These converters present their own challenges related to their construction, control, reliability and scalability. A series of secondary objectives may be incorporated as well; these may include reducing the switching frequency [13], [14], balancing power between cells [15], [16], reducing the common-mode voltage, or minimizing the output voltage’s jumps between non-
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