A high-voltage DC bias architecture implementation in a 17 Gbps low-power common-cathode VCSEL driver in 80 nm CMOS

Abstract

This paper describes a new, robust system-architecture for common-cathode (CC) vertical-cavity surface-emitting laser (VCSEL) drivers for highly-scaled CMOS technologies with low supply voltages. The concept implies converting the input signal into a current which is transferred to an amplifier built in a floating well by the level-shifter. Setting the potential of the well as high as the parasitic diode break-down voltage, a high DC bias voltage is possible for the VCSEL, several times higher than the gate-oxide break-down of CMOS technologies. The architecture is demonstrated with the design of a VCSEL driver in 80 nm CMOS with 1.2 V breakdown. The VCSEL DC bias can go as high as 4.5 V. The fabricated chip was bonded to a CC VCSEL. Electrical, optical and robustness measurements were performed. The optical eye was open until 17 Gbps at a bit-error-rate (BER) of 10−12 with only 60 mW power consumption including the VCSEL current. The driver met the electrical robustness evaluation offering a more reliable alternative to stacked CC architecture. The active area is of only 0.003 mm2, one of the smallest existing VCSEL diode drivers for this data-rate.