A High-Speed, Fully-Pipelined VLSI Architecture for Real-Time AES

Abstract

Nowadays, data encryption and decryption have become mandatory for any real-time communication applications. We propose a novel, area-speed efficient, high-speed architecture for the Advanced Encryption Standard hardware implementation. Our proposed architecture utilizes the composite field technique for SubBytes/InvSubBytes transformation instead of the traditionally-used look up table technique. As a result, the unbreakable delay of using look up tables in the traditional technique is eliminated. This, in turn, enables sub-pipelining implementation for further speeding up. Moreover, composite field arithmetic is employed to reduce the critical path delay. We propose a new algorithm to generate the optimum isomorphic mapping matrix, which reduces the critical path delay dramatically. In addition, an efficient key expansion architecture suitable for real-time applications is presented. Using the proposed architecture, a fully sub-pipelined implementation with 6 sub-stages in each round can achieve a throughput of 49.401 Gbps on a Xilinx XC2V6000FF1152-6 device in non-feedback mode, which is twice faster than the fastest Advanced Encryption Standard FPGA implementation known to date.